I just received notification from the guys and gals at Mentor that they will be holding the first webinar in a three-part series on 7 September 2011 at 9:00am to 10:00am US/Pacific, 9:00am to 10:00am ...

Alchip Technologies, Inc., the AI infrastructure and high-performance ASIC leader, today revealed significant development in its commercialization of 2nm customer devices. The company announced that ...

In one traditional model for ASIC development, a customer provides a set of chip performance specifications and the ASIC design house goes off and designs the ASIC on its own. However, when Emerson ...

NEC Electronics Corp. Monday unveiled its next generation 90nm ASIC platform, offering up to 4 million usable gates and clock speeds to 500MHz. Called ISSP2 (instant silicon solution platform), the ...

With the emergence of 90-nm process technology, ASIC designers get to explore uncharted levels of performance and density. However, it has also unleashed a slew of challenging design-integrity issues, ...

As AI workloads move from cloud to edge, the volume of image and sensor data across industries is rising rapidly. Edge devices that previously relied on FPGAs and off-the-shelf modules are now running ...

Rambus Sets New Benchmark for AI Memory Performance with Industry-Leading HBM4E Controller IP (March 5, 2026) Faraday Broadens IP Offerings on UMC’s 14nm Process for Edge AI and ...

Fraunhofer IIS brings decades of expertise in system and algorithm design, e.g. for high-performance computing, low-power wireless communication, and advanced sensor technology applications. By ...

Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, ...

ADTechnology says on the 23rd it pushes a strategic technology partnership with Germany's Fraunhofer Institute for Integrated Circuits to jointly develop 4-nanometer (nm, one hundred-millionth of a ...

As AI models and computing demands continue to grow exponentially, the biggest challenge in chip design is no longer pure processing power, but the bandwidth gap between processors and memory. Even ...