跳变延迟故障见图6，是指电路无法在规定时间内由0跳变到1或从1跳变到0的故障。在电路上经过一段时间的传输后，跳变延迟故障表现为固定型故障。 图6 跳变延迟故障 （5）传输延迟故障（Path Delay Fault） 传输延迟故障不同于跳变延迟故障，是指信号在特定路径 ...

集成电路测试的目的是希望在一批器件中找出有缺陷的器件，从而将交付的DPPM(每百万器件中的缺陷器件数目)降低至100以下。通过对自动测试图样生成(ATPG)算法进行一些设计修改，就可能在合理的测试图样数目下达到较高的缺陷覆盖率。本文描述了在评估不同 ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

传统的自动化测试模型生成(ATPG)技术没有直接定位对90纳米和以下工艺愈发重要的小延迟缺陷问题。Synopsys与日本半导体技术学术研究中心(STARC)合作开发出新型ATPG技术。 传统的自动化测试模型生成(ATPG)技术没有直接定位对90纳米和以下工艺愈发重要的小延迟 ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

WILSONVILLE, Ore., May 18, 2015 -- Mentor Graphics Corp. (NASDAQ: MENT) today announced that Mellanox Technologies has standardized on the new Mentor® Tessent® Hierarchical ATPG solution to manage the ...

MOUNTAIN VIEW, Calif. -- Oct. 5, 2015 -- Synopsys, Inc. (Nasdaq: SNPS) today announced a new, breakthrough ATPG and diagnostics technology that delivers 10X faster run time and 25 percent fewer test ...

The semiconductor industry has long relied on scan ATPG (automatic test pattern generation) tools instead of functional test to create stimulus-response patterns with very high fault coverage. But ...

Recent and continuing trends in the semiconductor industry pose challenges to IC test-data volumes, test application times, and test costs. The industry has thus far succeeded in containing test costs ...

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...