EDN

FPGA-Based FIR Filters using Distributed Arithmetic

M. Martinez-Peir, R. Colom, F. Ballester, and R. Gadea are teachers with a focus on digital applications at the Technical University of Valencia, Spain. They are currently working on video compression ...
Electronic Design

Digital ICs/DSPs: FIR Filter Tool Generates Low-Or High-Pass Options At Up To 160 MHz

The CoreFIR finite-impulse-response (FIR) intellectual-property (IP) core generator, the latest member of the DirectCore portfolio, is optimized for use with the company's flash- and antifuse-based ...
EDN

Platform FPGA design for high-performance DSPs

As DSP technologies find their way into high-end, high-complexity commercial and consumer applications, developers are discovering the limitations of traditional Digital Signal Processors (DSPs) to ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel ...

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Electronic Design

Digital Filter Design

Digital signal processors (DSPs) continue to receive a great deal of attention in new product design. For example, digital filter design reflects the importance of understanding and using this ...