SAN JOSE, Calif. -- October 1, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today received three TSMC Partner of the Year Awards during ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...

Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure Early customers seeing more than 2.5X design cycle ...

Cadence Design Systems CDNS announced that its digital and custom/analog flows had received certification on Intel's 16 FinFET process technology. Additionally, Cadence's design intellectual property ...

14-nanometer SOI FinFET Process Leverages Strong Ecosystem Partnerships Between EDA, Foundry and IP Providers to Deliver Significant Power Savings Potential SAN JOSE, Calif., 30 Oct 2012 - Cadence ...

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...

GUC utilized the Encounter Digital Implementation System to address the implementation challenges that arise at 16FF+, including increased double-patterning and FinFET design rule checking (DRC), ...

Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual (DRM) and SPICE ...

The next frontier in the electronics industry is the FinFET, a new type of multi-gate 3D transistor that offers tremendous power and performance advantages compared to traditional, planar transistors.