EDN

‘Best practices’ improve hierarchical design constraints

One of the key factors in the design and development of submicron chip designs is the setting of good physical and timing constraints, no matter what type of design methodology you use. Constraints ...
EDN

Hierarchical timing analysis: Pros, cons, and a new approach

As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain ...
Design-Reuse

Hierarchical design methodology supports complex FPGAs

FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...
Semiconductor Engineering

Efficient Hierarchical Verification For Low Power Designs

Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, ...