While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

“Golden” RTL code has been seen as a holy grail of IC design for many years. It promises to deliver code that is reusable in future designs. However, golden RTL is very difficult to achieve. Too many ...

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...