Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...

CAST, the semiconductor intellectual property provider, has unveiled the CAST Catalyst Program. This program is a new way for embedded system developers to adopt RISC-V processors faster and with less ...

IP that’s built on a RISC-V vector processing CPU. The platform has been augmented to support artificial-intelligence/machine ...

BANGKOK, Dec. 12, 2019 /PRNewswire/ -- RISC-V Summit -- The trend towards compute intensive gateways and edge devices is driving the integration of traditional deterministic control applications with ...

India has formally introduced DHRUV64, a 64-bit, dual-core microprocessor based on the RISC-V instruction set, developed by the Centre for Development of Advanced Computing (C-DAC) under the national ...

It’s pretty neat to flash firmware on a microcontroller thousands of miles away and see the development board blink in response. We’ve covered the Open-V before, and the crowd funding campaign they ...

As microchips increasingly become an integral part of our lives, share prices for many companies that make them are rising fast. Last week shares of NVIDIA Corp (NVDA) jumped over 30%, pushing its ...

June 8, 2021 Nicole Hemsoth Prickett Compute Comments Off on AI Is RISC-V’s Trojan Horse into the Datacenter If the workload-specific datacenter dominates in the near term, it could be RISC-V’s time ...

If you wanted to make a CPU, and you’re not AMD or Intel, there are two real choices: ARM and RISC-V. But what are the differences between the two, and why do companies choose one over the other?

The third annual RISC-V summit takes place next month, 8-10 December 2020, and like the majority of events this year, will be completely online. The program features three days of talks around ...

This blog will look at recent developments in RISC-V and in particular at announcements by Western Digital at the 2018 RISC-V Summit in Santa Clara, CA. RISC-V is an open, scalable instruction set ...