Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D ...

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

Scan technology was developed as a structured test technique that divided the complex sequential nature of a design into small combinational logic blocks that could be tested individually. This added ...

With increasing numbers of ASICs finding their way into high-volume products, production testing of these devices must be fast, complete, trouble-free, and economical. To achieve these goals, ...

In the mid 80s, a group of industry pioneers, the Joint Test Action Group (JTAG), started meetings in a hotel near the Amsterdam airport, invited by Philips, to put down the first stone of one of the ...