With 68% of the ASICs going through respins and 83% of the FPGA designs failing the first time around, verification poses interesting challenges. It’s also not a secret that nearly 60-70% of the cost ...

New research paper titled “Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification” from researchers at University of Bristol and Infineon Technologies. “Constrained ...

ROHM Semiconductor today announced it has released the ROHM PLECS Simulator on ROHM’s official website. This simulation tool enables designers of power electronics circuits and system designers to ...

Axiomise’s Nicky Khodadad and Ashish Darbari discuss simulation and the need for formal verification and RISC-V, including why simulation-based verification is inadequate to find all the bugs in a ...

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...

Completing Clock Domain Crossing Verification. Nvidia wanted a methodology for complete clock domain crossing verification ...

The title of this article may sound like the start of a Seinfeld joke from the 90s, but it’s actually a serious question. Many people do not appreciate what makes a system-on-chip (SoC) different from ...