With the rapid move to ultradeep submicron designs and feature size processes of 0.13 micron and below, ensuring the integrity of signals as they traverse conductors on a chip is becoming a challenge.

Santa Cruz, Calif. – Claiming the first hybrid approach to transistor-level timing and crosstalk analysis, Nassda Corp. this week will introduce Hanex, a product that combines static and dynamic ...

Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper ...