SAN JOSE, Calif. — Simple assertions should be part of future Verilog IEEE standards, according to panelists at the DVCon Design and Verification Conference here Monday (Feb. 24). But several said ...

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...

Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA ...