Munich, Germany – Transaction-level modeling got a hard look at the recent Design Automation and Test in Europe (DATE) conference here as a possible answer to some of the design and verification ...

Transaction-level modeling (TLM) verification methodologies are propagating down from power users, such as large systems houses and integrated device manufacturers, to the broader design community. As ...

After years of working at the register-transfer level, chip designers and verification engineers are warming up to a new approach that may represent the next step up in abstraction. But it's not a ...