Santa Cruz, Calif. — Analog and custom IC designers' wait for transistor-level statistical timing analysis at 65 nanometers and below may be coming to an end. Two recent announcements promise that the ...

Solido Design Automation (Saskatoon, Saskatchewan, Canada) wants to help analog and full-custom digital designers glean more insight from the statistical-analysis step of the traditional tool flow ...

A new technical paper titled “Dual-Layer Thin-Film Transistor Analysis and Design” was published by researchers at Oregon State University and Applied Materials. “A set of analytical equations is ...

Efinix turned to the Siemens mPower power integrity analysis platform to obtain the capabilities they needed for fast, accurate, full-chip EM/IR analysis of their Titanium FPGA designs. With no ...