针对 Versal 器件的设计流程增强： 控制内核在 AI 引擎阵列中的相对布局，从而提升性能，提高利用率。 强化面向 Versal® ACAP 设计的配置与调试功能，包括死锁检测、较大布线数据采集、RTL/Python 测试平台支持。 Vitis 集成设计环境下的异构设计的新仿真选项。

Xilinx unveiled its Vitis AI software platform back in late 2019, to simplify development for the company’s chip-level hardware architectures and accelerators, using common software development tools ...

SAN JOSE, Calif., Oct. 1, 2019-- XILINX DEVELOPER FORUM (XDF) AMERICAS 2019 - Xilinx, Inc. (NASDAQ: XLNX), the leader in adaptive and intelligent computing, today announced Vitis™ (pronounced Vī-tis), ...

The VCK5000 uses the Xilinx VC1902 Adaptive Compute Acceleration Platform (ACAP), which combines an FPGA, system-on-chip (SoC) processor complex, and hardware acceleration (Fig. 2). The entire ACAP ...