Semiconductor Engineering

Singulated Die Test Ensures Stacked Die Quality As Power Density Rises

The high power density in turn produces large thermal gradients, with the low to max temperature changes increasing dramatically in both mission mode and test mode as process geometries shrink, as ...
Semiconductor Engineering

Need For KGD Drives Singulated Die Screening

The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...
Business Wire

Hprobe Announces New Generation of Magnetic Test Head for Wafer Sort of MRAM in Mass Production

GRENOBLE, France--(BUSINESS WIRE)--Hprobe, a provider of turnkey semiconductor Automatic Test Equipment (ATE) for magnetic devices, today announced a breakthrough magnetic test head revolutionizing ...
Electronic Design

Reducing Logic Device Test Costs

Test-flow partitioning between wafer sort and final package test can have a dramatic impact on the cost of test. In some cases, the migration of package tests can be done over time, but the test ...
EDN

Contactless Testing Wafer Testing

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announced the successful production of the world’s first semiconductor wafer whose ...
New Electronics

ICsense expands ASIC production capacity with new wafer sort cleanroom

The new facility forms part of ICsense’s latest strategic investment programme and is intended to support growing demand for custom ASIC solutions across multiple industries. The global ASIC market is ...
Hosted on MSN

Japanese chipmaker Rapidus begins test production of 2nm circuits — company commits to single-wafer processing ahead of 2027 mass production target

Rapidus on Friday announced that it had begun prototyping of test wafers with 2nm gate-all-around (GAA) transistor structures at its IIM-1 facility in Japan. The company confirmed that early test ...